Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs
نویسندگان
چکیده
منابع مشابه
Large multipliers with less DSP blocks
Recent computing-oriented FPGAs feature DSP blocks including small embedded multipliers. A large integer multiplier, for instance for a double-precision floatingpoint multiplier, consumes many of these DSP blocks. This article studies three non-standard implementation techniques of large multipliers: the Karatsuba-Ofman algorithm, non-standard multiplier tiling, and specialized squarers. They a...
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Multiplication functions constitute the kernel of many real-life applications. They are used extensively in applications such as digital signal processing, image processing, cryptography and multimedia [1,2,3]. Recent computing oriented FPGAs feature embedded DSP blocks including small embedded multipliers. Achieving efficient realization of multiplication may have significant impact on the spe...
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Multipliers have a significant impact in the performance of the entire Dsp system. Many highperformance algorithms and architectures have been proposed to accelerate multiplication without increasing the hardware. In previous papers, the truncation error is reduced by adding error compensation circuits. In this paper, truncation error is not more than 1 ULP (unit of least position). So there is...
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ژورنال
عنوان ژورنال: International Journal of Reconfigurable Computing
سال: 2009
ISSN: 1687-7195,1687-7209
DOI: 10.1155/2009/145130