Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs

نویسندگان
چکیده

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Large multipliers with less DSP blocks

Recent computing-oriented FPGAs feature DSP blocks including small embedded multipliers. A large integer multiplier, for instance for a double-precision floatingpoint multiplier, consumes many of these DSP blocks. This article studies three non-standard implementation techniques of large multipliers: the Karatsuba-Ofman algorithm, non-standard multiplier tiling, and specialized squarers. They a...

متن کامل

ECE 734 Project Proposal Exploring realizations of large integer multipliers using embedded blocks in modern FPGAs

Multiplication functions constitute the kernel of many real-life applications. They are used extensively in applications such as digital signal processing, image processing, cryptography and multimedia [1,2,3]. Recent computing oriented FPGAs feature embedded DSP blocks including small embedded multipliers. Achieving efficient realization of multiplication may have significant impact on the spe...

متن کامل

Exploring realizations of large integer multipliers using embedded blocks in modern FPGAs

An efficient design methodology and a systematic approach for the implementation of multiplication for unsigned large integers, using small-size asymmetric embedded multipliers is presented. Three different approaches are explored for the design. A general architecture of the multiplier is proposed and a set of equations is derived to aid in the realization. The inputs of the multiplier are spl...

متن کامل

Design and Implementation of Signed, Rounded and Truncated Multipliers using Modified Booth Algorithm for Dsp Systems

Multipliers have a significant impact in the performance of the entire Dsp system. Many highperformance algorithms and architectures have been proposed to accelerate multiplication without increasing the hardware. In previous papers, the truncation error is reduced by adding error compensation circuits. In this paper, truncation error is not more than 1 ULP (unit of least position). So there is...

متن کامل

Performance Analysis of Different Multipliers for Embedded and DSP Applications

This Paper presents an efficient implementation of high speed multiplier using the shift and add method, Radix_2, Radix_4 modified Booth multiplier algorithm. In This paper we compare the working of the three multipliers by implementing each of them separately in FIR filter. The parallel multipliers like radix2 and radix4 modified booth multiplier does the computations using lesser adders and l...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: International Journal of Reconfigurable Computing

سال: 2009

ISSN: 1687-7195,1687-7209

DOI: 10.1155/2009/145130